is VHDL unsafe with state machine?

Nice thread. One comment to Tricky's post that registers will power-up to 0 unless otherwise stated. Note that they always power-up to 0. If you have a reset that says it should come up as 1, then a not gate is put before and after the register. So the register still powers up to 0, but it immediately gets inverted so it looks like a 1 to the rest of the world. As data goes through, it is inverted coming in and going out, so the rest of the design is unaware. Not gates are free in most conditions, as they can be absorbed into the LUT.

So for a one-hot state machine, it actually comes up as all 0s. You'll see it like so:

000

011

101

As you can see, the LSB is basically inverted. Most users are never aware of this, but the two places it comes up are timing simulations and signaltap, where in both cases you are looking at the register between the not gates, so it will look like its acting the opposite of what you'd expect. This really doesn't have a whole lot to do with the thread, but hopefully interesting.