is VHDL unsafe with state machine?

I think your question confuses several unrelated points. In functional simulation, the initial state of a signal will follow general VHDL rules, not an assumed behaviour of FFs. For enumerations, the first member is the initial state.

In synthesized code, there's no thing like unknown state. Safe coding of state machine doesn't mean to enter an 'X' state for a missing reset. It means that any illegal states will automatically cause a transition to a defined, usually the initial state. That's important to prevent locking of a FSM in case of unexpected events, e.g. clock glitches or timing violation of input signals.

A functional simulation however does neither show nor handles illegal states, you have to refer to a gate level simulation to check for these effects.

In my opinion, there's no principle difference between VHDL and Verilog implementation of state machines, except for some syntax details. But although you'll define e.g. a state encoding in Verilog, it will be usually translated in a one state hot design by the synthesis tool.