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Altera_Forum
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14 years ago

is VHDL unsafe with state machine?

Typical VHDL state machine is to define a type that consist of states, then use that type in a signal. But if someone (not me, no way! ;-)) forget to put a reset state, the state machine continues to...
Altera_Forum's avatar
Altera_Forum
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14 years ago

no they shouldnt. By default ALL registers in an FPGA powerup to '0' unless specified. Whether you code in Verilog or VHDL it wont be any different. There is no such thing as undefined in real hardware. Even more interesting, a state machine like this with more than 3 states has the states encoded as 1 hot by default, so there are actually many illegal states.

As for the VHDL, all types, if left uninitialised, will initialise to the left most state, which in this case is S0. It cannot go to 'X' in simulation because you have not defined an 'X' state. This is not a std_logic (which would default to 'U', not 'X'). If you really want the specifics, then yes, you have to define the states yourself using std_logic_vector or similar. Even if you did this, without the reset, its likely to power up to all zeros, regardless of what youir first state should be.

The solution: have your powerup/reset state as the left most state.