Is this already maximally pipelined ... anything I can do to speed this up?

First of all, I will commend that your code is not too clear. Why are you comparing the counter to a signed version of 0? why is the counter signed? so all you need to check is the MSB of counter.

Also, its not obvious that you are checking if e is greater than 0. Be explicit to be clearer.

How big is e? if it is more than 3 bits, you could do the compare to 0 (or you can OR all of the bits in the bus) in a previous cycle, then OR the 1 bit value with the counter compare result.

Other than that, it is about as efficient as you can get.

Remember, that the datasheet is idealised maxed speed. So this will be zero/minimal delay to the logic inputs. In reality, this will never happen. I dont know what chip you are using, but 300MHz would be fairly reasonable.

Bare in mind that if this is your top level design, then it will be routing to the logic from device pins, which will likely be quite a delay as the DSPs are not near the pins. Try setting the logic pins to virtual to remove this delay.