Is there any way to pre-load the Altera DDR3 (Uniphy) Memory Model?

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This model is written in system verilog and although I've identified the array it doesn't show up in Modelsim and so there must be some trick to pre-loading it.

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The array is there, it just might not look how you might have expected it to look :)

The 'mem_data' is a System Verilog associative array which means it is sparsely populated. Within ModelSim "Memory List" window, it is only going to have a size corresponding to the elements which have been populated (memory data written into them). So when you first start the testbench, it has size zero instead of e.g. 128M filled with x's if you're familiar with an older SDRAM model.

The Altera models have "MEM_INIT_EN" and "MEM_INIT_FILE" parameters that you can use to have the SystemVerilog execute loops to load that data from a file. You just need to modify the generated files to set MEM_INIT_EN=1 and supply a valid file.

Or, you can leave those parameters as-is (MEM_INIT_EN=0) and then at an appropriate time with your testbench execution, you can use the ModelSim "mem load" command to change the contents of the array.

For example,

VSIM> cat x.mem
#  // memory data file (do not edit the following line - required for mem load use)
#  // instance=/x_tb/x_inst/mem_if_ddr3_mem_model_0/depth_gen/width_gen/mem_inst/rank_gen/rank_inst/mem_data
#  // format=mti addressradix=h dataradix=s version=1.0 wordsperline=1
#   0: 11101111
#   1: 10111110
#   2: 10101101
#   3: 11011110
#   2048: 11101111
#   2049: 10111110
#   204a: 10101101
#   204b: 11011110
#  
#   5555: 11101111
#   
VSIM> mem load -i x.mem {/x_tb/x_inst/mem_if_ddr3_mem_model_0/depth_gen/width_gen/mem_inst/rank_gen/rank_inst/mem_data}
VSIM> mem display -addressradix hex {/x_tb/x_inst/mem_if_ddr3_mem_model_0/depth_gen/width_gen/mem_inst/rank_gen/rank_inst/mem_data}
#   0: 11101111
#   1: 10111110
#   2: 10101101
#   3: 11011110
#   2048: 11101111
#   2049: 10111110
#   204a: 10101101
#   204b: 11011110
#   5555: 11101111