Forum Discussion
Altera_Forum
Honored Contributor
11 years agoThanks for the data Alex. I was referring specifically to the Altera DDR3 (Uniphy) Memory Model, which is a model of external memory instantiated via Qsys to simulate off chip memory to simulate the Altera DDR3 Uniphy Controller. This model is written in system verilog and although I've identified the array it doesn't show up in Modelsim and so there must be some trick to pre-loading it.