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DNewm1's avatar
DNewm1
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5 years ago

Is there any way to connect a signal to a PLL in a Max 10 without using a dedicated clock input?

Customer has protos built already but did not route clock signals to dedicated clock inputs, and they need to use the PLLs. Is there any way at all to get to the PLLs from regular I/O? Or from the ...
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi Danny

In general, the reference input clock signal to the PLL must be driven by the dedicated clock input pin located adjacent to the PLL, or from the clock output signal from the adjacent PLL. Input and output delays are only fully compensated for when the dedicated clock input pins associated with that specific PLL are used as the clock source.

If the clock source for the PLL is not a dedicated clock pin for that specific PLL, jitter will increased, timing margin suffers, and the design may require an additional global or regional clock.

Thanks.

Eng Wei

DNewm1's avatar
DNewm1
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5 years ago

Thanks Eng Wei.

A follow up and more specific question: is there a legal way to connect a signal to a PLL in a Max 10 without using a dedicated clock pin. I forgot to mention that the build fails in the fitter if any input signal from a pin other than a clock pin is connected to the PLL in a max 10 device.