DNS00New Contributor6 years agoIs there any issue, when the data bus connected between FPGA and MCU, both side are in input state at a particular stage
1 ReplyReplies sorted by Most Likedak6dnRegular Contributor6 years agoNope. Just turn on the 'bus hold' feature on the FPGA inputs so the bus lines don't float and/or possibly oscillate.
ak6dnRegular Contributor6 years agoNope. Just turn on the 'bus hold' feature on the FPGA inputs so the bus lines don't float and/or possibly oscillate.
Recent DiscussionsLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.
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