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JET60200's avatar
JET60200
Icon for Contributor rankContributor
5 years ago

Is there an 10GE example design available for A10 Device ?

Is there an 10GE example design available for A10 Device ? We need this to verify 10GE Serdes Functionality on A10SOC board. Also I'm not very familar to 10GE testing method, so if some recommenda...
SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

This is correct for channel 0, this is same as TX0p and RX0p, for TX0n and RX0n, the Quartus will auto-assign, and you can find it from the Fitter report -> Plan Stage -> Input Pins /output Pins,

set_location_assignment PIN_BC7 -to tx_serial_data[0]

set_location_assignment PIN_AW7 -to rx_serial_data[0]

Regards -SK

  • JET60200's avatar
    JET60200
    Icon for Contributor rankContributor
    5 years ago

    Thanks @ SK , get it.

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    I just wonder SI Board has only one SFP+ hardware interface, but the Example generate two SFP+ i/f , which introduce a bit confusion. Anyway I understand yet.

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    Thanks for quick response

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    best regards