Is there an 10GE example design available for A10 Device ?

Thanks @SengKokL_Intel​ ,

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Sory but I'm really a newbie to FPGA world!!

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I have checked the ug-20016 "4. 10GBASE-R Ethernet Design Example for Intel Arria 10" ,and tried to generate an design example using the Platform Designer (with Quartus Pro 19.2).

And this generated project can be compiled ok in Quartus Pro 19.2. But in Platform designer, I select "No development kit" option.

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I have a Intel A10SOC Evaluation Board on hand, and If I wanto run my 10GE test project on it ? HOw should I do in next step ?

（ I guess I should assign the correct pin-assignmnt in my project according to A10SOC Board, anythings else ? ）

Thanks in advance

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Hello SK, thanks for guidance, :) May I ask a more question ?

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I follow ​"ug-20016.pdf" to generate a "10GBASE-R Ethernet Design Example" for Arria 10" in Platform Desigher ( Pro 19.2) , and in Target Board field, I select " GX Transceiver Signal Integartion Development KIt ", I can generate example and compile it OK. Then I open the “altera_eth_top.qsf" to check what's its appropriate Pin Assignment ？

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I dowload schematics from "Arria 10 GX Transceiver Signal Integrity Installation Package (Production Edition)" from link: https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-a10-gx-si.html, But I found some discrepancy.

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1) in Design Example "altera_eth_top.qsf ", the SFP+ connector pin assigns are below, : PIN_BC7、AW7 , _BD5、_BA7 ,

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set_location_assignment PIN_BC7 -to tx_serial_data[0]

set_location_assignment PIN_AW7 -to rx_serial_data[0]

set_location_assignment PIN_BD5 -to tx_serial_data[1]

set_location_assignment PIN_BA7 -to rx_serial_data[1]

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2) But from the schematics of " A10 GX Transceiver Signal Integartion Board" and its user guide, the SFP+ PIN is obvious diferrent :

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Table 5-15: SFP+ Interface Connector (J29)

Signal Net Name Pin Number Description

GXBR_4C_TX0p BC7 GXB transmit

GXBR_4C_TX0n BC8 GXB transmit

GXBR_4C_RX0p AW7 GXB receive

GXBR_4C_RX0n AW8 GXB receive

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SO WHY THE example pin assignment are different to Board Shcematics ? What's the problem hete ? Thanks in advance .

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/Best regards

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