Is there a way to specify an forwarded clock as the clock source for input delays

The virtual clock you need should really be CLK_IN_virt, the clock that is driving the ADC to generate the data incoming to the FPGA. Are you saying that the output clock from the FPGA is what is controlling this? If so, this is referred to as a data feedback design. The SDC should look something like this:

# define input and pll clocks
create_clock –name clk_in –period 10.00 [get_ports clk_in]
derive_pll_clocks
 
# define generated output clock to be used as ASSP clock
create_generated_clock –name clk_out -source [get_pins {pll|clk[0]}] /
	[get_ports clk_out]
 
# define false path on output clock port
set_false_path –to [get_ports clk_out]
 
# define input delay constraints based on clk_out from FPGA
set_input_delay –clock clk_out –max 6 [get_ports datain*]
set_input_delay –clock clk_out –min 2 [get_ports datain*]

CLK_OUT becomes the launch edge for the incoming data and the 100 MHz clock capturing the incoming data becomes the latch edge. Replace the input delay values as appropriate.

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