Forum Discussion
Nooraini_Y_Intel
Frequent Contributor
7 years agoHi TGrev,
The Quartus programmer does not use BSDL file to detect the FPGA or CPLD devices. The programmer is built with its own database to detect the device in JTAG chain. All the device IDCODE information can easily be found from respective FPGA & CPLD device handbook under the JTAG Boundary Scan Testing chapter. There is no reason to keep a list on all device IDCODE information as there will always be newer devices being develop where its device handbook will cover this information.
Regards,
Nooraini