Forum Discussion
JBoot1
New Contributor
New ContributorIs it possible to use the FLR for the HIP PCIe AVST core to reset logic?
I have an endpoint design which uses the hard IP PCIe avalon-st core with multiple functions. One of the functions is used by a VM so I would like to enable the function level reset for that functi...
SengKok_L_Intel
Regular Contributor
Regular ContributorThe bits that relate to FLR are located at Device capabilities register (bit 28), and Device control register (bit 15) as per the PCIe spec.
In the Cyclone V PCIe AVST user guide, it is mapping to the PCIe Capability Structure (table 8-8), however, the FLR is not supported in Cyclone V PCIe AVST, the IP may not respond with it at all.
Regards -SK
JBoot1If the FLR is not supported in the Cyclone V PCIe AVST, then why are there parameter bits available in Platform Designer to enable it on a per function basis?
