Is it possible to use the FLR for the HIP PCIe AVST core to reset logic?

The document you referenced states that part of the sequence the host writes the FLR bit in the Device Control register. My logic does have access to this register, so I think I can create my logic reset by monitoring that bit. The only question that remains is which bit is it? My references don't specifically define that, nor am I surprised since the PCIe spec doesn't require support of FLR. So I assume Intel has mapped one of the reserved bits in either what they call cfg_dev_ctrl_func<n> or cfg_dev_ctrl2. Does this sound feasible? Can you provide the bit mapping for the control registers?