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To all FPGA Gurus,
Is it possible to study and design the controller for SATA2/3, USB2/3 and DDR2/3 in 2 months, without using the extremely costly IP core with time limit?
I just realised that a good SATA3 IP core somehow cost 3x higher than the DE4v530. Honestly, it is heart breaking.
Because it seems that if the company folks can do it, why not ourselves?
Does anyone experience/knowing where to get the resources of the functional block diagram or the operating sequences of these high speed interfaces?
(I don't believe I can't make it from scratch, though :p)
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Hello everyone.
Some years ago there was an open-source project implementing an USB client (USB 1.1, 1.2 MBit low-speed only) on the GPIO lines of an 8-bit microcontroller.
For me this means implementing an USB core should not be too time intensive if you are already familiar with USB internals (these can be downloaded but you need a lot of time reading and understanding it).
Martin
Honored Contributor
