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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Is it possible to configure Agilex-F P-Tile to have a PCIe Gen4 X4 EP port and a Gen4 X4 RP port?

Hi, The document of "Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express Design Example User Guide", ug-20268, page#3 shows the design example does not support the Gen4 X4 EP port. Is it limi...
  • seanw_skhms's avatar
    seanw_skhms
    5 years ago

    Hi,

    Thanks for the helps.

    I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

    Thanks.

    Xiao

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Xiao,


Yes, can. You may leave the unuse port not connected. I did a quick compile by only connect either Port 0-3 or Port 4-7, there is no compilation error. And also, I did not do any pin assignment, the Quartus will help to place it to the right location.


Regards -SK


  • seanw_skhms's avatar
    seanw_skhms
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    Thanks for the helps.

    I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

    Thanks.

    Xiao