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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
Solved

Is it possible to configure Agilex-F P-Tile to have a PCIe Gen4 X4 EP port and a Gen4 X4 RP port?

Hi, The document of "Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express Design Example User Guide", ug-20268, page#3 shows the design example does not support the Gen4 X4 EP port. Is it limi...
  • seanw_skhms's avatar
    seanw_skhms
    5 years ago

    Hi,

    Thanks for the helps.

    I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

    Thanks.

    Xiao

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Xiao,


It looks fine to me. You may start with a simple design and only assign the pin for port 4-7 and determine whether there is any abnormality from the Quartus compilation.


Regards -SK


  • seanw_skhms's avatar
    seanw_skhms
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Let me try it out later. But currently I stuck in generating the RP IP.

    Does the routing tool consider it as an error for unassigned ports at lane#0-3 and lane#8-15? Actually the PHY locations for these unused lanes are fixed and the pad location can be assigned automatically by the routing tool (other company's fpga tool does like this). I worry that the RP port on lane#0-3 could be active still?

    Regards,

    Xiao