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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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Is it possible to configure Agilex-F P-Tile to have a PCIe Gen4 X4 EP port and a Gen4 X4 RP port?

Hi, The document of "Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express Design Example User Guide", ug-20268, page#3 shows the design example does not support the Gen4 X4 EP port. Is it limi...
  • seanw_skhms's avatar
    seanw_skhms
    5 years ago

    Hi,

    Thanks for the helps.

    I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

    Thanks.

    Xiao

SengKok_L_Intel's avatar
SengKok_L_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Xiao,


1) There is a hardware limitation in the x4 core where it does not enable for EP, this is the same for R-Tile. See table 12 below.

https://www.mouser.do/pdfDocs/ag-overview.pdf


2) The “bifurcation mux” in table 57 is supported in v20.2, there is a plan to update this document in the next release.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avmm.pdf


3) In a single P-Tile, it can only support either EP or RP. Both EP and RP are unable to configure in a single P Tile at the same time.


Regards -SK


seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Got it. Interested in the "4 X4" configuration shown in the Table-57, mentioned in the answer-2.

In our design, we just want to active the X4 RP port on the lane#4-7 driven by the X16 core, and to disable the X4 RP ports connected to the other lanes (lanes#0-3 and lanes#8-15). Is it doable? Especially, we want to disable the PHY on lane#0-3, when the X4 RP port on lane#4-7 is running.

Thanks,

Xiao