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seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago
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Is it possible to configure Agilex-F P-Tile to have a PCIe Gen4 X4 EP port and a Gen4 X4 RP port?

Hi, The document of "Intel FPGA P-Tile Avalon Memory Mapped IP for PCI Express Design Example User Guide", ug-20268, page#3 shows the design example does not support the Gen4 X4 EP port. Is it limi...
  • seanw_skhms's avatar
    seanw_skhms
    5 years ago

    Hi,

    Thanks for the helps.

    I misunderstood your words of "only assign". Actually you mean "only connect", which makes sense for me. I will try it soon, and right now I am struggling on generating the RP IP.

    Thanks.

    Xiao

seanw_skhms's avatar
seanw_skhms
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi,

Thanks for the information. Dose it mean the two X4 cores in the P-Tile can not be configured into EP mode? Where is the limitation coming from? It looks like this limitation is also applying for the PCIe Gen5 interface in later Agilex-I R-Tile?

The document shows the Quartus tool will support user to configure the "bifurcation mux" in future version. When will it be available?

I do not see the answer if it is possible to configure one core in EP mode and other one in RP mode? Since the Avalon-MM bridge is built in user fabric, it should not be a problem to support mixed EP and RP modes.

Thanks,

Xiao