Forum Discussion
Altera_Forum
Honored Contributor
18 years agoNow to the point raised by the prior post, agreed, the external logic is committed to the IO pins, and as such, one could most likely design internal reprogrammable functions that could adaptively mutate their functions under NIOS II control, effectively achieving partial reconfiguration (of sorts) without the need to fully reload the entire FPGA array.
It just depends on what you are trying to do, the time frame you are (need) to get it done in, and how parallelly expansive you allow your mind to think (float). Avatar