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Honored Contributor
Honored ContributorIQ down converting speed
I need some advice on device speeds. I want to implement a simple IQ down converter. A simple test taking an input signal from an A/D (6 clocks to read), & mixing it with an NCO, implemented in a...
Altera_ForumHonored Contributor
Honored ContributorFPGA based digital signal processing generally uses pipelined datapathes, latency times don't affect the throughput. This is also the case with pipelined high speed ADC.
You can generally assume, that FPGA based DSP can handle data streams up to the ADC sampling rate, if the required interface is supported by the respective FPGA family. The faster core and periperals of Stratix family eases the design of DSP at speeds of 100 MHz and above. In so far, design economy may suggests to choose high performance FPGA. But 100 MHz sampling rate can be handled by Cyclone designs as well.
