Altera_ForumHonored Contributor13 years agoI/O states in Cyclone III in JTAG mode Hello all, In Altera's application notes it is specified that during JTAG mode all I/O pins are tristated. It is sometimes mentioned that the weak pull ups are enabled when the I/O pins are t...Show More
Recent DiscussionsCyclone-V SCFIFO - adding ECC to M10K/MLAB/Auto memoryWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File Information