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Altera_Forum
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14 years ago

I/O states in Cyclone III in JTAG mode

Hello all, In Altera's application notes it is specified that during JTAG mode all I/O pins are tristated. It is sometimes mentioned that the weak pull ups are enabled when the I/O pins are t...
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Altera_Forum
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14 years ago

If by "JTAG mode" you mean the period while you configure the FPGA through JTAG then yes, on recent FPGA famillies the I/O pins are tristated and the weak pull-ups are enabled.