invert clock at output pin in DDR3 uniphy controller

Hi, Alex, thanks much for your reply.

i read the open code, the ck/ck# is generated by altddio->altio_buf, it seems i can invert the signal, but as you said, it influence internal timing and quartus indeed gives timing violation warnings. i am now trying to find where i can invert clock safely, but you know it is not easy.

As the option in board setting you advised, i think that cannot solve my problem, for addr/ctrl/cmd routing are all ok, just ck/ck# is swapped, i think the 'Maximum CK delay to DIMM/device' indicates ck/addr/ctrl/cmd as a group, well, i will try this option to see what happens.

For we have added external series resisters for clocks, so we can debug our board cross soldering the resisters.

however, i do interested in solving this problem in the fpga logic.

there is an option 'addtional ck/ck# phase' in wizard, which i think could solve the problem, but unfortunately it is grayed.

en, if altera guru knows how to fix it, please kindly help.

Life is hard, we are working hard on it.

Best Wishes,

ingdxdy