invert clock at output pin in DDR3 uniphy controller

I think this will depend on which pins your DDR3 clock comes from. They typically come out on the dedicated 'PLL_OUT' pins, directly from the low latency PLL output signals. Assuming they do then there's no method of inverting them between the PLL and the pins.

If they don't come out of these dedicated pins then you should be able to invert them. However, this has further implications as the delay out of the device will be far less determinate and may well compromise the DDR functionality in a different way.

In the UniPHY there is an option, in the 'Board Settings' tab, to specify the 'Maximum CK delay to DIMM/device'. You could try adding half your clock period to whatever value you have in there. This may cause a change to the PLL settings to work in your favour. I hope this would change the relative position of the clock at the start of DDR3 training and, hopefully, allow the UniPHY and PLL to find a working solution.

I would also say this is worth asking Altera directly about as well. Open a case through myAltera. They seem to be on the case at the minute...

Cheers,

Alex