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Altera_Forum's avatar
Altera_Forum
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9 years ago

invert clock at output pin in DDR3 uniphy controller

Hi, I am using DDR3 uniphy controller in startixV(with Quartus 15.1). In PCB board design, the clock is mistakely swaped at output, that is, ck at fpga pin is connected to ck# at ddr3 pin. ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

thanks for your reply.

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Are you using Hard DDR-3 Controller or Soft?

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i am using soft ddr3 ip core(with quarter rate mode).

Best Wishes,

ingdxdy