Forum Discussion
EBERLAZARE_I_Intel
Regular Contributor
6 years agoHi ranran,
I could not find the specific example, but we do have a GPIO example showing how to handle the interrupts for DE10 nano:
https://software.intel.com/en-us/articles/explore-gpio-example-application
The FPGA design illustrates how the programmable logic can be used to extend the peripherals available to a processor.
- RShal46 years ago
Occasional Contributor
The issue been solved.
For anyone with similar problem try the following:
- check which type of interrupt is used level or edge in the pio (check in qsys), if it's edge, the HPS GIC should handle it as edge !
- it is required to clear edge interrupt in PIO, by writing into PIO edge "edgecapture" (edge detection bit)
- It is also required to be sure that writing the PIO works, i.e. required first to enable LWH2F , and best to check in memory view that the registers are read/written correctly (without enabling the bridge it won't do anything)
- if all above does not work, better to verify with signaltap what happens in irq signal.
Thanks