Forum Discussion
Hi,
Yes. The uc/os based example can be downloaded from here:
https://www.micrium.com/download/de10-nano_webserver/
it catch timer and serial interrupts from HPS side, I just added the code above to catch interrupt 72, and 73, which should be for FPGA2HPS irq 0 and irq 1.
I remembered to load DE10_NANO_SoC_GHRD.sof into FPGA before running the HPS example.
If you download the terrasic cd (from here https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1046&PartNo=4), there is a folder DE10_NANO_SoC_GHRD, which contains qsys of the project, from there I can see that interrupts 72,73 are given from FPGA to HPS and are routed to KEY0 and KEY1 on board. I also tried to change qsys with interval timer instead of KEY0 but got the same behavior.
I also tried with another OS - code-time, which also has a demo for DE10, and I also added 2 lines for setting and enabling interrupt 72,73. But in this case I even didn't get the 1st interrupt ( code-time demo can be given after a request from code-demo support).
But again, maybe I miss something very basic in the process ?
I also very surprised that I can't find ANY baremetal example which show how to catch interrupt which comes from fpga to HPS !!
I hope you can help with it, because a whole project depends on this capability.
Thank you for any idea
ranran