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Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Interpretation of compiler report

Hi, I am new with Quartus designs and have following questions to compiler reports. There are no errors but many warnings. 1) I designed a schematic with the block editor. Compilation for a MAX3000A...
Fpga Devkit
Programmable Logic Device
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

I don't see a clock input in the part of your schematic you attached unless you're talking about "TRGI". The target should be whatever you've named it in the design. If it's TRGI, use that.

VHDL code has nothing to do with this. The tool interprets the schematic directly.

Niko3's avatar
Niko3
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

In my former post I had attached a further image showing the clock input of my schematic but it was not transfered.

I try it again hoping that it will be transfered now.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hi,
    if it's the top level schematic, the clock pin name is set to "CLK" by applying the name to the pin symbol. It has to be referenced in get_ports.
  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    So, yes, it should be [get_ports CLK] in your create_clock command.

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