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Altera_Forum
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16 years ago

internal differences in fpga when using sstl_2(or sstl_18) class i and ii io standard

i am using cyclone ii fpga to interface to ddr ram. by the handbook of cyclone ii, it's top and bottom banks support sstl_2 class i and ii io standards. so what's the internal differences(just at ...
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Altera_Forum
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16 years ago

Two remarks anyway:

"Turning on" OCT at the FPGA side is refering to dynamic OCT with Stratix III etc.

Using 25 ohm OCT respectively 16 mA with SSTL class I results in an impedance mismatch, so I won't generally suggest it. But it can be helpful to improve the usable RAM speed in some cases, at least for short FPGA-to-RAM connection lengths.