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Altera_Forum
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16 years ago

internal differences in fpga when using sstl_2(or sstl_18) class i and ii io standard

i am using cyclone ii fpga to interface to ddr ram. by the handbook of cyclone ii, it's top and bottom banks support sstl_2 class i and ii io standards. so what's the internal differences(just at ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

No SSTL interface circuit uses external series resistors. They always rely on the internal driver impedance. It should be also mentioned, that most SSTL interface variants don't achieve exact impedance matching. It's important to have some termination to avoid multiple reflections. The best solution would be dynamic OCT at both sides, but it's not available for Altera FPGAs below Stratix III.