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Altera_Forum
Honored Contributor
8 years agoHi Hondabones
1.Do you mean DCLK? 2.Is timing constrains met? 3.Is both board having same design(schematic/board) Even board trace can add capacitance and introduce timing variations. 4.Check the operation after rest the design. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)