interleave two ad9288 to cyclone iii

What the FPGA will have as inputs will be 4 separate bus, each 8 bit wide and operating at 125 MHz.

That, it can handle.

Now.. if you want to interleave the data from the 4 channels inside the FPGA then it depends on how you'll do it.

Do you really need to handle the data stream using 8 bit wide, 500 MHz logic blocks?

That's pretty much NOT possible.

Or can you parallelize your processing and the clock, ie handle 32 bit wide vectors and use only a 125 MHz clock?