Interfacing to epcs64 from fpga

Your MSEL setting suggests you're ultimately going to configure the FPGA from the EPCS, in AS mode. Is that right? Have you tried this? This would at least prove the board. You can program the EPCS using JTAG Indirect Configuration (.jic), via the FPGA, if you don't have direct programming access to the EPCS.

Have you constrained the I/O to connect all the pins, including the EPCS pins, as you require? You need to do this - don't assume Quartus knows simply because you've used an EPCS. An FPGA will happily support multiple EPCS devices connected to different sets of I/O, not just the config pins. It sounds like the ASMI IP is functioning but it's clearly not connected to the I/O you intend.

Some FPGA's need you to specifically tell Quartus that you want access to an EPCS device, from the fabric, when it's connected to the FPGA's configuration pins (I don't recall specifically for Stratix IV). Check under 'Device and Pin Options' -> 'Dual-Purpose Pins'.

Following a reset, with the board connected as you describe, you should see nCS assert (LOW) and DCLK toggling as the FPGA attempts to configure from the EPCS. You suggest 'DCLK - constant low' and nCS deasserted. This doesn't sound right to me. However, you say you can configure the FPGA via JTAG. This setup and these observations don't stack up.

Cheers,

Alex