Interfacing the FPGA to a micrcontroller

Hi,

You can set the output port to high impedance when the chip select from the MCU is high/low(depends on the active level). For example:

reg  reg_calc_data;
wire  databus;
assign databus= (chipselect) ? reg_calc_data : 8'bZZZZZZZZ; 

For the data availability you can use a dual port fifo ram.

Here is some example http://www.asic-world.com/examples/verilog/asyn_fifo.html

Quartus has a build in Megafunction for FIFO memory. Take a look at the megafunctions documentation.

Best regards,

VT