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Because cyclone V does not support BLVDS
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Not completely right. AN522 suggests to use Differential SSTL-2 to implement BLVDS with Cyclone V.
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if DDR's are 4n prefetch then bandwidth is 200 MHz x 32b x 4 = 25 600 Mbit/s.
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Can't follow your calculation. DDR is double data rate, not quad data rate. In addition, you can stream out a full row continuously, but some housekeeping and setup of next transfer has to be performed. Expect e.g. 95% of burst transfer rate for large blocks. Performing concurrent read and write will further halve the bandwidth.
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