interface object "USB_RD_N" of mode out cannot be read

Thanks for explaining your statement. As you can try yourself, none of the said restrictions applies to Quartus VHDL compiler, even though it's officially based on VHDL 1993.

I'm not sure, how a buffer port is treated by the Xiliinx tools, but with Quartus, an output signal is always read before feeding the IO-cell (except for INOUT port, of course), so there's no difference between an internal signal and a signal read from a buffer port. I guess, the respective warning in the Xilinx paper may be also inappropriate for their tools, but it's not my concern.

The other point, addressed both in the Xilinx paper and vhdl 2008- just the new stuff is a restriction in the VHDL specification on the connection of components with buffer ports in the upper entity, that is said to be in effect before VHDL 2002. I must confess, that I wasn't aware of it yet, because it's apparently ignored by Quartus. Also the ModelSim versions I've been using didn't have it.

So all in all, compatibility with other tools may require to avoid buffer ports, but there's apparently no problem with the Quartus VHDL compiler (at least since V5.0).