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Altera_Forum
Honored Contributor
15 years agoIn theory a buffer is different from an out port, in practice the compiler may treat them alike (although our friends at Xilinx warn us : http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html (http://www.xilinx.com/itp/xilinx4/data/docs/sim/coding4.html)). Peter Ashenden and Jim Lewis explain the subtle difference in their book: "VHDL-2000-8 Just The New Stuff", pages 162 to 165.