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Altera_Forum
Honored Contributor
15 years agoOr switch to VHDL 2008. In VHDL 2008 an out port behaves as a buffer port and output ports can be read back internally.
Alternatively, in VHDL 1993, define a local signal which is used internally, and assign this signal to the output port. This is what I used to do, until VHDL 2008, which has a lot of other goodies too. Beware that VHDL 2008 is only partially implemented in QII 9.1SP2. QII 10.0 looks a lot better (but there I am missing the internal simulator, but that's an entirely other thread).
entity smth is
port (
...
portname : out std_logic ;
...
) ;
end smth ;
architercture a of smth is
....
begin
...
signal local_portname : std_logic ;
...
process( ...)
begin
...
local_portname <= ...
...
end process ;
portname <= local_portname ;
end a ;
Using a buffer in stead of an out just to fix the reading back issue is not recommended.