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mreca's avatar
mreca
Icon for New Contributor rankNew Contributor
6 years ago

Interface LVDS signals to the FPGA cyclone V GX.

Few weeks ago I aquire the cyclone V GX starter kit, we are working in a project using the AFE5809evm to receive data from a array of ultrasound sensors, the AFE do all the signal digitalize and...
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi Mateo, First of all, you need to determine the location of the LVDS pin on the development kit which is connected to the HSMC. Then. in Intel Quartus Prime software, assign that pin to output / input and you can use Intel LVDS IP to deserialize the signal and process it using your own RTL. Hope it helps. Regards, YL