interface a module with avalon bus

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Hi Phlibi, I read over your code, it can help understand how to interface avalon Bus but at first glance it has some flaws:

Registers are 32 bit wide-

No byte addressing is provided on

No status register is provided to check for overflow

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This is left as an exercise for the reader ;) In fact, this component does not serve any real purpose anyways, so I've just omitted additional features. Byte addressing would need additional consideration anyways, as this would basically lead to kind of vector processing by packing four independent additions into one word or something similar.

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On avalon write part:

if reset = '1' then

dac_value <= (others => (others => '0'));

elsif rising_edge(clk) then

this code reset an undeclared dac_value, I don't see declared on your code post, others is used two times as if op_a was an aggregate so I think about syntax error, IMHO it has to reset op_a and op _b so must look as it follow --- :

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Yeah, dac_value is a relict from where I copied the code from. This was some other component from one of my designs and I just overlooked the line when hacking in the modifications. As I said, I haven't tested it.

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this version generate an asyncronous reset and probably a latch.

if rising_edge(clk) then

if reset = '1' then

op_a <= (others => '0');

op_b <= (others => '0');

else

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Yes, this would be the proper reset code.

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Process calc is active forever, it is required just when you write one of operand, this save a lot of power.

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This is an FPGA, not a microcontroller where you can just "skip" an operation when it's not used. The adder is needed anyways, so it will always draw static power. As long as the input data doesn't change, there is no additional dynamic power. The only thing which is always clocked is the result register, but adding additional logic to enable it only when something changed will most likely increase consumption. I doubt that any of these would actually be measurable, though.

Bye,

Philipp