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Altera_Forum's avatar
Altera_Forum
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18 years ago

Intelligently synthesizing a constant coefficient FIR filter

Here's a question:

Is QuartusII intelligent enough to synthesize a constant-coefficient FIR filter using logic resources instead of multipliers (DSP blocks)? I have a test design that implements a 32-tap FIR configured as such. The coefficients are literally VHDL "constants".

Thanks,

-dB

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Quartus integrated synthesis has rules for which things to implement automatically in DSP blocks (and similarly in RAM blocks). There are synthesis directives and Assignment Editor assignments for user control of this. If you are getting DSP blocks automatically, then in the Assignment Editor try setting "Auto DSP Block Replacement" to "Off" or setting "DSP Block Balancing" to "Logic Elements".