Altera_Forum
Honored Contributor
8 years agoIntel HLS Compiler [Could not link 'vsim_auto_compile.so']
Hey,
I am attempting to get the 'hls multiplier example' to work using Quartus Prime 17.1 running Ubuntu 17.10. After troubleshooting I have been able to get ModelSIM working and fixed the broken PATHs defined in init_hls.sh. After running: source init_hls.sh and make in the example folder I get the error '** fatal: ** error: (vsim-3828) could not link 'vsim_auto_compile.so'. Any help would be greatly appreciated: here is the relevent section of the log file generated by Quartus/i++ (the entire file exceeded the character post limit):*******************************************************
i++ debug log file
This file contains diagnostic information. Any errors
or unexpected behavior encountered when running i++
should be reported as bugs. Thank you.
*******************************************************
Compiler Command: i++ -I/usr/include/c++/4.8.5 -I/usr/include/c++/4.8.5/x86_64-linux-gnu -I/usr/include/x86_64-linux-gnu/c++/4.8 -L/home/themajesticbaker/intelFPGA_lite/17.1/hls/linux64/lib/dspba/linux64 -march=CycloneV mult.cpp -o fpga.exe
# ** Warning: (vsim-3015) tb/simulation/submodules/acl_push.v(151): - Port size (1) does not match connection size (8) for port 'data_out'. The port definition is at: tb/simulation/submodules/acl_token_fifo_counter.v(38).# Time: 0 ps Iteration: 0 Instance: /tb/mymult_inst/mymult_internal_inst/mymult_internal/themymult_function/thebb_mymult_B0_runOnce/thebb_mymult_B0_runOnce_stall_region/thei_acl_push_i1_wt_limpush_mymult/thei_acl_push_i1_wt_limpush_mymult3/genblk1/genblk2/fifo File: tb/simulation/submodules/acl_token_fifo_counter.v# Compiling /tmp/themajesticbaker@themajesticbaker_dpi_4807/linuxpe_gcc-4.7.4/exportwrapper.c# ** Fatal: ** Error: (vsim-3828) Could not link 'vsim_auto_compile.so': cmd = '/home/themajesticbaker/intelFPGA_lite/17.1/modelsim_ase/gcc-4.7.4-linux/bin/gcc -shared -fPIC -m32 -B/usr/lib32 -o "/tmp/themajesticbaker@themajesticbaker_dpi_4807/linuxpe_gcc-4.7.4/vsim_auto_compile.so" "/tmp/themajesticbaker@themajesticbaker_dpi_4807/linuxpe_gcc-4.7.4/exportwrapper.o" '# (vsim-50) A call to system(/home/themajesticbaker/intelFPGA_lite/17.1/modelsim_ase/gcc-4.7.4-linux/bin/gcc -shared -fPIC -m32 -B/usr/lib32 -o "/tmp/themajesticbaker@themajesticbaker_dpi_4807/linuxpe_gcc-4.7.4/vsim_auto_compile.so" "/tmp/themajesticbaker@themajesticbaker_dpi_4807/linuxpe_gcc-4.7.4/exportwrapper.o" >'/tmp/questatmp.gnw5S6' 2>&1) returned error code '1'.# The logfile contains the following messages:# /home/themajesticbaker/intelFPGA_lite/17.1/modelsim_ase/gcc-4.7.4-linux/bin/../libexec/gcc/i686-pc-linux-gnu/4.7.4/ld: /usr/lib32/crti.o: unrecognized relocation (0x2b) in section `.init'# /home/themajesticbaker/intelFPGA_lite/17.1/modelsim_ase/gcc-4.7.4-linux/bin/../libexec/gcc/i686-pc-linux-gnu/4.7.4/ld: final link failed: Bad value# collect2: error: ld returned 1 exit status# # No such file or directory. (errno = ENOENT)# # # FATAL ERROR while loading design# ** Error: Error loading design# Executing ONERROR command at macro ./tb/simulation/mentor/msim_compile.tcl line 8# End time: 09:38:40 on Feb 06,2018, Elapsed time: 0:00:08# Errors: 4, Warnings: 7