emrahenerNew Contributor3 years agoIntel Agilex FHT / FGT lane swapping Hi, We are using AGILEX AGIB027R31B2E2V FPGA . For Implementing 100 G Ethernet we utilize 4 FHT lane (4x25) Bank 13C Rx / Tx rx/tx_serial port Lane 0 connected to FHTR13C RX/TX CH0 . When I i...Show More
jmcguire3Occasional Contributor2 years agoBump. F-tiles appear to have bus-twist issues in Quartus. More info here:https://community.intel.com/t5/Programmable-Devices/Agilex-F-Tile-bus-reversal-twist/m-p/1559892#M94136
Recent DiscussionsIssue with configuring EPCQ64A & Cyclone10LP using NiosV as processor.Error with PDN Tool 2.0 for Cyclone VTrouble Getting started with Stratix 10 SOCSolvedJTAG Chain Broken on Agilex 7-I Dev KitAgilex 5 Power