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Altera_Forum
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14 years ago

Integer to Bit Vector VHDL code error

I'm new to VHDL and I am trying to convert an integer to a 14 bit vector. Here is the protion of my code. gear_calc <= to_integer(unsigned(to_stdlogicvector(Input_2))); synchro_g...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Port maps can have unsigned/signed type or even integers in them, you dont have to stick with std_logic/std_logic_vector, or even worse, bit vectors, especially if its an embedded entity (ie not directly connected to pins). For the top level its best to stick to some array type, but you can still use unsigned/signed to avoid all that annoying type conversion.