Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

inserting delay buffer at output pin of FPGA

hi all, I want to add a small delay to one of my outputs, just to test/try out an idea. I need about 10-15ns, while my clock is 204ns period. Looking around the web, I see some people using ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Using an additional tap from the PLL sounds like a reasonable option, and also will be compensated across voltage and temperature. If you go and insert logic in the path, you will get very different delays between slow and fast corner since the effect of process voltage and temperature in CMOS circuits varies greatly.