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Honored Contributor
Honored Contributorinserting delay buffer at output pin of FPGA
hi all, I want to add a small delay to one of my outputs, just to test/try out an idea. I need about 10-15ns, while my clock is 204ns period. Looking around the web, I see some people using ...
Altera_ForumHonored Contributor
Honored ContributorPerhaps one way to do it is to create a second clock with a pll that has the same period but is phase shifted by 10ns. Output A can be clocked on the initial clock's edge, while output B can be clocked on the phase shifted clock's edge. This way output A will update 10 ns prior to output B.
