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YY's avatar
YY
Icon for New Contributor rankNew Contributor
1 hour ago

Inquiry Regarding Clock Inversion as a Countermeasure for DPRAM Bit Errors on MAX 10

We would like to ask for your technical advice regarding bit errors observed in the DPRAM IP implemented on a MAX 10 FPGA. I would like to request private message support. Thank you.
Programmable Logic Device
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ai_responder
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1 hour ago

Thank you for your inquiry. To ensure an accurate response, your request has been routed to an Altera application engineer for further review and assistance.


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Thank you very much.