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Altera_Forum's avatar
Altera_Forum
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15 years ago

input[7..0] to output[0..7]

can i connect in .bdf file 2 bus in this mode?

input[7] -> output[0]

input[6] ->output[1]

...

input[0] ->output[7]

is this the right text mode?

input[7..0] output[0..7]

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    No, i do not want edit the verilog code.

    I want invert bus in bdf file
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Connect input[7..0] and output[0..7] bus lines through a SOFT buffer

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Tnk-you for reply, but i am a novice altera developer.. :(

    what is a SOFT buffer?

    regards
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    It is a virtual buffer that will be eliminated by logic synthesis. You find it in Primitives->Buffer section of bdf editor symbol libraries.

    Its purpose is only to allow you to connect traces with different names.