Input problem for PLL block

You will not be able to implement a multiplexer on the input to the PLL without an external loop. However, this introduces noise - something the PLL doesn't like.

In addition, in specifying the PLL parameters you are specifying the input frequency. If you then chose one of a number of different frequency clocks then you end up working outside the input frequency range of the PLL you've designed. This may well work but I wouldn't recommend this.

If you're intending to use multiple clocks of the same frequency but different phases - that's OK. However, multiplexing one of these internally and routing it back externally is very likely to introduce different delays to each clock, which will in turn ruin the phase shifted clocks you had to start with.

As Kaz suggested, generate multiple PLL outputs and operate from one of them via a mux.

Regards,

Alex